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Tilera 100-core CPU said 4X faster than new Xeons

Tilera TILE-Gx100 may beat Intel

Tilera on Monday unveiled a new processor it hopes will unseat Intel from its overall lead in performance. The TILE-Gx100 counts on a massively parallel, 100-core architecture to handle many tasks at once and reportedly overcomes some of the problems of scaling inherent to many-core designs. Instead of using a data bus, the grid is treated as a mesh network with switches on each core to route data smoothly. The approach lets Tilera reach the core count without it stalling or without the added space dictated by the bus architecture.

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Mac Pro to get exclusive on six-core, 32nm Xeons?

Apple may get early use of Gulftown Xeon

Apple may have a temporary exclusive on Intel's fastest workstation Xeons early next year, a purported leak argues tonight. An unnamed source says Apple is readying a Mac Pro based on the Xeon version of Intel's Gulftown six-core architecture and that the Mac builder would have a short exclusive for the processors, launching its own workstations in the winter while everyone else would have to wait until the spring. What configurations would ship aren't known by the MacBidouille tipster.

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Intel to demo Larrabee, Sandy Bridge tomorrow

Intel Maloney keynote leaked

A prematurely released copy of Intel's plans for a Wednesday keynote has surfaced a day in advance and has provided details of the company's plans for the near future. The release obtained by ZDNet has Intel executive VP Sean Maloney revealing that the company has started shipping its many-cored Larrabee graphics chip to developers ahead of a full release and demonstrating what it can do in real-time. The demo should show a custom build of the online shooter Enemy Territory: Quake Wars running with raytraced lighting, a feat which is technically difficult for any graphics hardware as it calculates the path of each ray of light rather than making "shortcut" calculations.

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Intel producing 32nm CPUs, "Jasper Forest" Xeons

Intel 32nm and Jasper Forest enroute

Intel on Monday headed up its Developer Forum with word that it has started manufacturing its first processors based on a 32 nanometer (nm) process. The shrink from 45nm, nicknamed Westmere, should improve performance by increasing the density of the processors by about 30 percent while reducing the amount of power used; the gesture lets Intel boost clock speeds without drawing extra battery life or generating more heat.

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Apple to use two new NVIDIA platforms?

Apple and MCP89 MCP99

Apple will not only move on to a newer NVIDIA platform for its notebooks but may include a second chipset, insiders claimed on Friday. Those purportedly within the notebook business tell DigiTimes that Macs will use MCP89, the successor to the existing GeForce 9400M (MCP79), but also that the company will use MCP99, a largely unknown second part. Other sources posting today suggest that MCP89 will be used for Core 2 mobile processors while MCP99 would be targeted at Nehalem-based Core i5/i7 processors and their eventual 32 nanometer successors under the future Westmere architecture.

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Sandy Bridge processors slated for Q4 2010 release

Sandy Bridge in Q4 2010

Intel has scheduled the release of its 32nm Sandy Bridge processors for the fourth quarter of 2010, according to DigiTimes. The architecture will succeed Nehalem and its condensed 32nm version, Westmere, the latter of which is set to be released in the fourth quarter of 2009. Sandy Bridge supports 4GHz clock speeds, with scalable CPUs using up to eight cores. The architecture also houses CPUs and GPUs on one die, unlike the two-die approach taken with Nehalem.

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Intel's 6-core Xeon spotted, detailed

Intel Westmere Spotted

Intel's six-core Xeon processor, known as Westmere, has been seen in a leak of an engineering sample today [caution: may not be safe for work). Still identified as a mainstream Core i7 chip by software, the Xeon W5590 example runs at a relatively low 2.4GHz clock speed but has 12MB of Level 3 cache shared between all cores and 256KB of Level 2 cache for each core. With Hyperthreading, which runs up to two program threads on a single core, the system shows as many as 12 effective cores.

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Intel provides early 32nm processor details

Intel Westmere Details

Intel at the International Solid-State Circuits Conference today provided some of the first concrete details of Westmere, the codename for its 32 nanometer processor family. The design is primarily a smaller, more efficient adaptation of the Nehalem architecture in the Core i7 but, in the dual-core desktop (Clarkdale) and notebook (Arrandale) offerings, will include both a two-channel DDR3 memory interface and an integrated but switchable graphics core. Like NVIDIA's Hybrid SLI mode or AMD's Hybrid CrossFire, the technology will let systems with dedicated graphics chipsets revert to Intel's own core in low-demand situations or when on battery.

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Intel to invest $7B in US-based, 32nm plants

Intel $7B plant investment

Intel President and CEO Paul Otellini on Tuesday announced the chipmaker will make its biggest ever investment for a manufacturing process for its 32 nanometer chips. The plan is to spend $7 billion on retrofitting existing production plants to build the new chips in the US over the next two years. The manufacturing plants due for the upgrade are based in Oregon, Arizona and New Mexico and will create about 7,000 jobs across the three states.

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Leaked Intel slides show 8-core CPUs, AVX

Intel 2009-1010 Leaked Map

Intel's upcoming processor generations will double the number of cores per chip and add a brand new language for specialized code, according to leaked slides obtained by CanardPlus. Although the semiconductor company's Core i7 will just receive a manufacturing process shrink down from 45 nanometers to 32 during 2009, reducing its power use and allowing more complex parts, a replacement architecture codenamed Sandy Bridge will replace it by 2010 and double the number of cores per die to eight. Hyperthreading support will let it handle as many as 16 code threads at once, while a large 16MB pool of Level 3 cache will be shared to make best use of the cores.

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