09/22, 6:00pm
Intel Maloney keynote leaked
A prematurely released copy of Intel's plans for a Wednesday keynote has surfaced a day in advance and has provided details of the company's plans for the near future. The release obtained by ZDNet has Intel executive VP Sean Maloney revealing that the company has started shipping its many-cored Larrabee graphics chip to developers ahead of a full release and demonstrating what it can do in real-time. The demo should show a custom build of the online shooter Enemy Territory: Quake Wars running with raytraced lighting, a feat which is technically difficult for any graphics hardware as it calculates the path of each ray of light rather than making "shortcut" calculations.
more
09/22, 2:05pm
Intel demos 22nm at IDF
As part of its Developer Forum keynote, Intel today showed the first working example of chips built on a 22 nanometer (nm) process. The process is even smaller than the 32nm technology just entering production and should run even more efficiently while fitting more into a given space. A single example chip about the size of a fingernail contains about 2.9 billion transistors and about 364 megabits (45.5MB) of static RAM.
more
08/12, 4:55pm
Sandy Bridge in Q4 2010
Intel has scheduled the release of its 32nm Sandy Bridge processors for the fourth quarter of 2010, according to DigiTimes. The architecture will succeed Nehalem and its condensed 32nm version, Westmere, the latter of which is set to be released in the fourth quarter of 2009. Sandy Bridge supports 4GHz clock speeds, with scalable CPUs using up to eight cores. The architecture also houses CPUs and GPUs on one die, unlike the two-die approach taken with Nehalem.
more
08/14, 1:55pm
Intel 2009-1010 Leaked Map
Intel's upcoming processor generations will double the number of cores per chip and add a brand new language for specialized code, according to leaked slides obtained by CanardPlus. Although the semiconductor company's Core i7 will just receive a manufacturing process shrink down from 45 nanometers to 32 during 2009, reducing its power use and allowing more complex parts, a replacement architecture codenamed Sandy Bridge will replace it by 2010 and double the number of cores per die to eight. Hyperthreading support will let it handle as many as 16 code threads at once, while a large 16MB pool of Level 3 cache will be shared to make best use of the cores.
more
