11/10, 9:05am
Intel Haswell to lower ultrabook power, up others
First details of Intel's Has well architecture has emerged through presentation slides leaked [reg. required] through ChipHell. The 22-nanometer design will focus most on Intel's promises of more advanced ultrabooks and will lower the peak power of a dual-core, low-voltage chip to 15W, helping battery life in systems like the MacBook Air. It should also support low-power DDR3 memory and get integrated GT3 graphics that, like on Sandy Bridge, are faster than on the desktop.
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09/13, 2:25pm
Intel Haswell to make huge strides in battery life
Intel at its Developer Forum provided more details about its Haswell processor foundation for 2013. Although 22 nanometers like the Ivy Bridge design due early next year, it will be much more power efficient than an existing chip. The company plans for a 30 percent reduction in active power use over a modern Core i5 and that notebooks could last a complete 24 hours on a charge without needing extended cells, competing with ARM tablets.
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05/31, 12:05am
Intel ultrabook idea based on MacBook Air concept
Intel's Sean Maloney opened Computex in earnest with a keynote hoping to redefine the ultraportable notebook class. Now calling them "ultrabooks," Intel saw them as systems that were under 0.8 inches thick but could still start under $1,000. The category included systems like the ASUS UX21 and, by extension, the MacBook Air.
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08/14, 1:55pm
Intel 2009-1010 Leaked Map
Intel's upcoming processor generations will double the number of cores per chip and add a brand new language for specialized code, according to leaked slides obtained by CanardPlus. Although the semiconductor company's Core i7 will just receive a manufacturing process shrink down from 45 nanometers to 32 during 2009, reducing its power use and allowing more complex parts, a replacement architecture codenamed Sandy Bridge will replace it by 2010 and double the number of cores per die to eight. Hyperthreading support will let it handle as many as 16 code threads at once, while a large 16MB pool of Level 3 cache will be shared to make best use of the cores.
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