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Intel launches first six-core processors

09/15, 3:20pm

Intel Xeon 7400

Intel this afternoon fulfilled a promise and launched the Xeon 7400. The processor once nicknamed "Dunnington" is the first x86 architecture design to hold six cores and is targeted at very high-end computing where sheer parallelism is more important than clock rate; it's particularly useful for virtual machines and databases, Intel suggests. The chipmaker estimates a speed boost of as much as 50 percent and helps this in part by a similar increase in Level 2 cache to 16MB as well as dedicated virtualization features on the cores themselves.


Intel's six-core Xeon 7400 due Sept. 15

09/04, 10:55am

Intel Xeon 7400 Leak

Intel's first processor with more than four cores will launch within less than two weeks, a leak from within the industry claims. The architecture previously codenamed Dunnington technology should start shipping on September 15th as the Xeon 7400 series and will carry its planned six cores, helping out with particuarly demanding computing tasks, especially virtualization of multiple operating systems.


Intel elaborates on Larrabee, Nehalem, Dunnington

03/17, 4:55pm

Intel on Nehalem, etc.

Speaking to the press in a conference call, Intel has revealed more details on some of its upcoming processor technologies. Among these is "Larrabee," an upcoming graphics chipset; while it should be integrated into motherboards, as Intel has done with most such efforts, the company says it expects to produce dedicated cards, raising the specter of competition with NVIDIA and AMD/ATI. Larrabee processors should scale to the multi-teraflop level, and will use a global cache shared by all cores. Larrabee products should begin shipping in 2009.


Intel preparing six-core Dunnington processor

02/25, 1:35pm

Intel Dunnington, Nehalem

Information has purportedly leaked on two upcoming Intel technologies. Foremost is a new Xeon CPU codenamed "Dunnington," which is said to use three dual-core processors based on 45nm Penryn technology. The CPU should use a shared 16MB L3 cache, but each core pairing is described as having 3MB of L2 memory. The chip is further said to have a 1,066MTs interconnect, and thermal design power rated under 130W.



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