updated 05:10 pm EDT, Tue August 12, 2014
Advanced memory allocation, not widely implemented, affected by flaw
Intel has discovered a major bug (referred to as "errata") in some models of its new Haswell chipset releases. Problems with the chip's transactional synchronization extension (TSX) instruction set will be disabled by Intel in revisions of motherboard firmware by vendors. Little, if any, software uses the instruction set now, but the feature is expected to be widely implemented in software tailored for the Haswell-EP server chipset.
TSX is intended to speed up multi-threaded code through a series of memory management techniques. The errata implementation will allow the processors to continue to operate as normal, but TSX features will be disabled, which will likely slow development of the feature for now.
Haswell-EP server-oriented processor and Broadwell-Y mobile chips will still ship on time, but it is too late to implement the fix in silicon. The Tech Report claims that users will be provided a software patch to re-enable TSX, but at their own risk. Most users will not be affected by the errata, at least in the short term.