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AMD pulls back the curtain on its first ARM A1100 server chip

updated 03:12 pm EDT, Mon August 11, 2014

Specifications, technical details released for 'Seattle' ARM Cortex-A57 SoC

Today at Hot Chips in Cupertino, California, AMD announced some new details about its Opteron A1100 "Seattle" system on chip (SoC) for servers. The "Seattle" SoC, which is to be AMD's first ARM entry over the next three years, packs a lot of processing power into a 28nm chip with a total of up to eight ARM Cortex-A57 64-bit cores.

Both Anandtech and Tom's IT Pro reported a wealth of information on the SoC's architecture and specifications from the event. "Seattle" sets the eight 2GHz cores into pairs, giving each a shared 1MB of cache, for 4MB of total L2 cache. All cache is ECC-protected outside of the L1 instruction cache, which is parity-protected. The SoC also has 8MB of shared L3 cache, accessible by all of the cores.

The A57-based SoC also has dual memory channels, allowing for a total of 128GB of RAM in either DDR3 or DDR4 at 1866 MHz. Like the cache, ECC memory is supported. The chip supports small outline (SODIMM), registered (RDIMM) and unregistered (UDIMM) modules.

The A1100 also handles input/ouput (I/O) on chip, and is shared by the cores. AMD's SoC offers eight lanes of third-generation PCIe, eight SATA 3.0 ports, two 10Gbit Ethernet ports and a single 10/100/100 Ethernet port. Ethernet is handled by 10GBASE-KR controllers, which are generally seen in blade servers and other server enclosures for copper backplane connections.

Two secondary processors are included in the A1100, including a single Cortex A5 that acts as a system control processor. The control processor is in charge of system and power management for the SoC. It's also responsible for the initial configuration and boot. The control processor has its own memory, ROM, and 10/100/1000 Ethernet for external connectivity. The processor uses ARM's TrustZone technology and I2X, SPI and UART interfaces.

The second processor, a cryptographic coprocessor, is used separately as a "dedicated accelerator" for encryption, decryption, compression and decompression of several algorithms. Those algorithms include Advanced Encryption Standard (AES), Elliptic Curve Cryptographic (ECC), RA, Secure Hash Algorithm (SHA), Zlib compression and decompression, and includes a true hardware random number generation. The compressor can be used by the control processor for non-secure and secure processing, while the A57 cores can use it for non-secure processing.

AMD is offering a development kit for the Opteron A1100 now for $3,000. The kit only comes with a four-core version of the A1100 SoC according to Tom's, four DDR3 memory slots with 16GB of RAM and two Ethernet ports.

by MacNN Staff



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