updated 04:30 pm EST, Thu March 1, 2012
Simulator could reduce risk in chip design
Researchers at MIT have developed a software simulation tool that models the performance of multi-core chip designs with more accuracy than previously possible. The software, named Hornet, can analyze a potential chip design concept down to a single processing cycle and find flaws early. This promises to greatly reduce the risk in the costly chip design process.
Chip makers have improved performance by adding more and more processing cores to their chipsets. Currently, they are offering solutions with up to 12 multi-cores. As they add cores, the complexity of the flow of data between the cores grows, and with it, the difficulty of accurately evaluating the design for potential flaws. Hornet complements both current hardware and software simulation tools. It has the ability to simulate power consumption, communications patterns between cores, the processing times of individual tasks as well as memory-access patterns. The tool can evaluate a design idea with equivalent of 1,000 or more cores. Because it is software-based, it also can be reconfigured more easily to test different design concepts.