updated 12:40 pm EDT, Mon June 26, 2006
Intel debuts Xeon 5100
Intel today introduced its dual-core Intel Xeon Processor 5100 series, previously codenamed "Woodcrest," for the high-volume server, workstation, communications, storage, and embedded systems. The processors are based on the chip maker's Intel Core Microarchitecture, the same technology used by Apple in its new Intel-based Macs. Apple is expected to debut an Intel-based replacement for its Power Mac systems before the end of 2007, in line with its promise to migrate its entire line of Macs to Intel. The Cupertino-based company has already rolled out a complete family of notebooks featuring Intel chips, along with Intel-based eMac and Mac mini systems.
The Dual-Core Intel Xeon Processor 5100 series delivers up to 135 percent performance improvements and up to a 40 percent reduction in energy consumption over previous Intel server products, according to the company.
Based on Intel's 65-nanometer manufacturing process that further shrinks transistors and power consumption while boosting speed, the 5100 series is "drop-in compatible" as part of the company's "Bensley Platform."
The Bensley platform delivers new server technologies that include faster, more reliable memory technology called FB-DIMMs, Intel Virtualization Technology (Intel VT), Intel Active Server Manager (Intel AMT), and Intel I/O Acceleration Technology (Intel I/OAT).
Intel said it will ship the 5100 series at frequencies up to 3.0GHz with a 1.33GHz front side bus (FSB), as well as 4MB of shared L2 cache or memory reservoir between both cores. The 3GHz version will ship with a thermal design point (TDP) of 80 watts with all others rated at 65W. An even lower voltage version will ship in the third quarter at 2.33GHz and a TDP of 40 watts.
The Intel Core microarchitecture will power the new processors, but will also serve as the foundation for the company's forthcoming mobile and desktop products branded as Intel Core 2 Duo processors.
"Simply put, the Core microarchitecture is a technical marvel that is driving a new era of power efficiency without compromising on what can only be described as eye-popping dual-core 64-bit performance," said Pat Gelsinger, senior vice president and general manager of Intel's Digital Enterprise Group.
The multicore-optimized architecture features Intel Wide Dynamic Execution to deliver more instructions per cycle. The architecture also offers a wider execution core, allowing each core to complete up to four full instructions simultaneously using an efficient 14-stage pipeline for improved and more efficient data transferring.
The processors also include Intel "Advanced Smart Cache" that allow one of two processing units –- or cores -– to use the entire memory reservoir if necessary while the other is idle, as well as Intel Smart Memory Access that can "hide" memory latency and bottlenecks.