06/01/2006, 1:15pm, EDT
Thursday, June 1st
Prelim benchmarks on Core 2 Extreme
Both versions of the Conroe chip will have 4MB of shared L2 cache, although some of the lower-end models will only have 2MB of shared cache, according to the report. "Conroe is a four-wide architecture, so can issue four instructions per clock, as opposed to the three-wide used in NetBurst and Athlon 64 architectures. The Core 2 will also contain a full 128-bit wide SSE (Streaming SIMD Extensions) engine that can execute one SIMD instruction per clock." According to the report, Intel plans to ship a 3.2GHz Extreme CPU later this year, while a quad-core CPU for enthusiast desktops is expected sometime in Q1 of 2007.
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