Dual-core PowerPC G5

IBM's Microprocessor division is developing a , which will be used in workstations and servers sometime next year, according to eWEEK: Code-named "Antares," it will contain two processing units per chip, with each carrying its own execution core, Level 1 cache and storage subsystems including a Level 2 cache...It will use 16 stages for most fixed-point integer operations; 18 for most load-and-store operations; and 21 stages for most floating-point operations. VMX operations, which will take 19 stages, will be handled in the 970MP's AltiVec-compatible vector processing unit...With the longer pipelining, the 970MP will implement "instruction cracking," which can distribute code requests to each core, splitting certain recognized instructions into several internal and simpler operations."

by MacNN Staff